At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Job Title: Formal Verification Architect, PCIe & UALink Controllers Role Summary We are looking for an experienced Formal Verification Architect to lead the formal verification strategy for high-performance PCIe and UALink controller IP. The ideal candidate will combine deep formal verification expertise with strong protocol and microarchitecture knowledge. This is a hands-on technical leadership role responsible for defining verification architecture, identifying high-value formal targets, solving complex proof problems, and driving formal methods throughout the IP development lifecycle. Key Responsibilities Define the formal verification architecture and methodology for PCIe and UALink controller IP. Develop block, subsystem, and end-to-end formal verification strategies spanning: Protocol engines and state machines Transaction and packet processing Flow control and credit management Ordering and dependency rules Replay, retry, recovery, and error handling Arbitration, scheduling, and resource management Power/reset and initialization sequences Configuration and control logic Identify areas where formal verification can provide stronger coverage than simulation, especially for corner cases, deadlocks, livelocks, starvation, ordering violations, data integrity, and protocol compliance. Architect assume-guarantee, compositional, abstraction, and formal decomposition strategies for large and complex controller designs. Develop reusable SystemVerilog Assertions (SVA), properties, checkers, constraints, and formal verification IP. Drive convergence of difficult proofs through abstraction, cut-points, state-space reduction, invariants, partitioning, and proof-debug techniques. Work closely with RTL architects and designers to improve design-for-formal-verification and resolve architectural ambiguities early. Define formal coverage criteria and establish metrics for proof completeness, unreachable states, vacuity, assumptions, and coverage closure. Lead formal analysis of complex bug classes that are difficult to expose through constrained-random simulation. Establish the appropriate balance between formal, simulation, emulation, and system-level verification. Review verification plans and architecture specifications to identify formal opportunities and verification gaps. Mentor verification engineers and raise formal verification capability across the broader controller verification organization. Required Qualifications BS/MS/PhD in Electrical Engineering, Computer Engineering, Computer Science, or related field. Typically 15+ years of Verification experience, with significant hands-on formal verification experience of 5 years at least. Deep expertise in property-based formal verification of complex RTL. Deep knowledge of PCI Express, preferably PCIe 5.0/6.0/7.0 controller architecture and verification. Experience with UALink, CXL, UCIe, Ethernet, or comparable high-performance interconnect protocols Strong knowledge of: SystemVerilog and SVA Formal property development Assumption and constraint modeling Abstraction and decomposition Formal coverage and proof closure Counterexample analysis and debug Hands-on experience with industry formal platforms such as Cadence Jasper or Equivalent Experience applying formal verification to high-speed interconnect or networking controller designs. We’re doing work that matters. Help us solve what others can’t. Additional Jobs Equal Employment Opportunity Policy: Cadence is committed to equal employment opportunity throughout all levels of the organization. Read the policy(opens in a new tab) We welcome your interest in the company and want to make sure our job site is accessible to all. If you experience difficulty using this site or to request a reasonable accommodation, please contact [email protected]. Privacy Policy: Job Applicant If you are a job seeker creating a profile using our careers website, please see the privacy policy(opens in a new tab). E-Verify Cadence participates in the E-Verify program in certain U.S. locations as required by law. Download More Information on E-Verify (64K) Cadence plays a critical role in creating the technologies that modern life depends on. We are a global electronic design automation company, providing software, hardware, and intellectual property to design advanced semiconductor chips that enable our customers create revolutionary products and experiences. Thanks to the outstanding caliber of the Cadence team and the empowering culture that we have cultivated for over 25 years, Cadence continues to be recognized by Fortune Magazine as one of the 100 Best Companies to Work For.  Our shared passion for solving the world’s toughest technical challenges, our dedication to pushing the limits of the industry, and our drive to do meaningful work differentiates the people of Cadence. Cadence is proud to be an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to race, color, sex, age, national origin, religion, sexual orientation, gender identity, status as a veteran, basis of disability, or any other protected class.

Design Verification Architect.

more at Cadence.

Software Architect

Sr HR Representative

Senior Digital Verification Engineer

similar roles.

Technician III, Facilities (Night Shift)

Technician III, Facilities

Further Processing 1st Shift Line (1) Lead-Person Front-End - Camilla GA Plant

Sr Environmental Supervisor-New Holland, PA

Salesforce Solutions Architecture Director

Senior Salesforce Developer