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Cadence

HSINCHU 05, Taiwan

Software Architect.

SENIOR LEVELENGINEERING
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Job Title EDA Architect Engineer – Debug, Analysis & FPGA Prototyping Job Summary We are seeking a highly experienced Frontend EDA Engineer to lead the development of design debug, analysis, and visualization tools for simulation and emulation solutions. The ideal candidate brings deep technical expertise in large‑scale RTL/netlist handling, performance optimization, and customer‑driven tool development, with a proven ability to collaborate closely with leading semiconductor and system companies. Key Responsibilities Frontend Debug & Analysis (Primary Focus) Architect, design, and enhance frontend EDA tools for RTL/gate‑level debug, waveform analysis, and design visualization. Drive performance, capacity, and usability improvements for large‑scale SoC designs. Establish and maintain baseline performance metrics for interactive editing, debugging, and analysis flows. Lead investigation and resolution of complex customer design issues involving RTL, netlists, timing, and simulation data. Technical Leadership & Customer Engagement Act as a technical owner for key frontend initiatives, from concept through deployment. Partner closely with tier‑1 semiconductor and system customers to deliver high‑impact, production‑ready solutions. Provide technical mentorship to senior and junior engineers across global development teams. Translate customer requirements into clear technical roadmaps and executable plans. Required Qualifications MS in Computer Science, Electrical Engineering, or equivalent practical experience. 20+ years of experience in EDA tool development with strong emphasis on frontend debug/analysis. Deep understanding of RTL, netlist, simulation, and verification flows. Proven experience improving tool performance, scalability, and developer productivity. Strong software engineering skills (C/C++, data structures, performance profiling, large‑codebase development). Experience working directly with customers on complex design and tool‑flow challenges. Preferred Qualifications Hands‑on experience with Front end design debug platforms. Background in FPGA‑based prototyping or emulation systems for SoC validation. Experience leading cross‑site or multi‑disciplinary engineering teams. Track record of delivering order‑of‑magnitude improvements in performance or productivity. Patents or publications related to EDA, debug, or design productivity. We’re doing work that matters. Help us solve what others can’t. Additional Jobs Equal Employment Opportunity Policy: Cadence is committed to equal employment opportunity throughout all levels of the organization. Read the policy(opens in a new tab) We welcome your interest in the company and want to make sure our job site is accessible to all. If you experience difficulty using this site or to request a reasonable accommodation, please contact [email protected]. Privacy Policy: Job Applicant If you are a job seeker creating a profile using our careers website, please see the privacy policy(opens in a new tab). E-Verify Cadence participates in the E-Verify program in certain U.S. locations as required by law. Download More Information on E-Verify (64K) Cadence plays a critical role in creating the technologies that modern life depends on. We are a global electronic design automation company, providing software, hardware, and intellectual property to design advanced semiconductor chips that enable our customers create revolutionary products and experiences. Thanks to the outstanding caliber of the Cadence team and the empowering culture that we have cultivated for over 25 years, Cadence continues to be recognized by Fortune Magazine as one of the 100 Best Companies to Work For. 
Our shared passion for solving the world’s toughest technical challenges, our dedication to pushing the limits of the industry, and our drive to do meaningful work differentiates the people of Cadence. Cadence is proud to be an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to race, color, sex, age, national origin, religion, sexual orientation, gender identity, status as a veteran, basis of disability, or any other protected class.
Pay
Not stated
Where
HSINCHU 05, Taiwan
Work
Not stated
Type
Not stated
Posted
9 Nov, 2026
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