We are seeking an experienced engineer for SoC Static Timing Analysis for advanced semiconductor products. This role will own end-to-end Timing Constraints and Static Timing Analysis across complex designs, driving initial constraints development and timing correlation in early stages to final Timing Signoff for cutting-edge technology nodes. This role would work with implementation engineers from synthesis through final timing closure to close timing, including timing correlation, debugging failing timing paths, providing timing ECOs (automated and manual). The ideal candidate demonstrates technical timing and constraints expertise to close timing on a given design on silicon along with capability of using timing analysis tools to correlate timing and generate automate as well as manual timing fixes. Key Responsibilities 1. End-to-End Constraints and Timing Signoff Ownership Drive Timing Constraints Creation and Validation Work with Frontend, IP and DFT teams to Validate Constraints, Resolve timing issues Work hand-in-hand with Implementation owner(s) and Full Chip STA team to close Timing Timing Correlation and Timing Path Debug from synthesis through timing signoff Provide timing feedback during all design stages Create Automated and Manual timing fixes for implementation 2. Team Leadership & Organization Development Participate career development. Interface with Implementation owner(s) and Full Chip STA team. 3. Technical Strategy & Innovation Provide feedback to improve scalability, productivity, and design quality through methodology enhancements to leadership 4. Cross-Functional & Ecosystem Engagement Collaborate with Frontend, IP and DFT teams for Constraint Validation and Timing Issues Support post-silicon bring-up, yield improvement, and production ramp activities. Core Technical Expertise STA and signoff methodologies Timing ECO Generation (automated and manual) Constraints Development and Validation Advanced node implementation (≤ 16nm / 5nm) Scripting in Python, TCL, and Perl Familiarity with using AI to generate scripts Required Qualifications Bachelor’s or Master’s in Electrical / Electronics Engineering or related field 3-6 years of experience in ASIC / SoC Timing Analysis Strong knowledge of industry STA tools (Synopsys flows) Strong communication skills Preferred Qualifications Experience in high-reliability SoCs Exposure to AI-driven design methodologies and automation Why This Role Matters Timing closure of flagship SoCs at advanced nodes Direct impact on silicon success and product competitiveness More information about NXP in the United States... NXP is an Equal Opportunity/Affirmative Action Employer regardless of age, color, national origin, race, religion, creed, gender, sex, sexual orientation, gender identity and/or expression, marital status, status as a disabled veteran and/or veteran of the Vietnam Era or any other characteristic protected by federal, state or local law. In addition, NXP will provide reasonable accommodations for otherwise qualified disabled individuals. #LI-6692 NXP Semiconductors N.V. (NASDAQ: NXPI) enables a smarter, safer, and more sustainable world through innovation. As the world leader in secure connectivity solutions for embedded applications, NXP is pushing boundaries in the automotive, industrial & IoT, mobile, and communication infrastructure markets. For more information, visit www.nxp.com Bright Minds. Bright Futures. We believe that a key component to growing our business is to develop our people. To enable you to grow your career at NXP, we offer online and offline learning opportunities to help you develop some of your core and professional skills. Commitment At NXP. We recognize NXP is a powerful change agent as we continue to deliver innovative solutions that advance a more sustainable future. We remain steadfast in our commitment to sustainability and making measurable year-on-year progress. Also, we aim to create an inclusive work environment and we will not tolerate racism, discrimination or harassment of any kind. We have programs in place focused on diversity, inclusion and equality. Thank you for considering a career at NXP. To help you prepare for the different steps in our hiring process, see the following useful advice and tips. Are you already an NXP employee? Do not apply here. Instead, you must apply via our internal career page. Thank you for your interest in supporting our recruitment efforts. Please note that NXP operates under a strict Preferred Supplier List (PSL) for all recruitment activities. Any candidate profiles or resume submitted without a prior written agreement or explicit request from our Talent Acquisition team will be considered unsolicited. Such submissions will be deemed free of any obligations, and no fees will be paid by NXP or any of its affiliates, subsidiaries, or divisions - regardless of whether the candidate is hired, either coincidentally or otherwise. Thank you for your understanding.

Static Timing Analysis Design Engineer / Physical Design.

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