As a Layout Design Intern, you’ll work with experienced design and circuit engineers on the physical layout and verification of high-performance mixed-signal CMOS integrated circuits. You’ll build hands-on experience translating circuit designs into layouts, learning how layout choices can affect circuit performance, and using industry tools such as Cadence Virtuoso XL and Calibre.
You’ll have opportunities to ask questions, learn from teammates, and contribute at a level that fits your experience. You don’t need to arrive knowing every tool or technique.
This role does not offer visa sponsorship.
Responsibilities
- Create and refine analog and mixed-signal circuit layouts with guidance from design engineers.
- Help investigate layout issues and explore possible solutions.
- Collaborate with circuit and design engineers to support circuit performance.
- Learn how layout planning, integration, and routing work at the block and chip levels.
- Get exposure to verification workflows and tools such as Cadence Virtuoso XL and Calibre.
- Explore techniques used for device matching and signal conditioning and protection.
Required Skills and Qualifications
- Enrolled in a bachelor's master’s or PhD program in computer science, computer engineering, electrical engineering, or related field.
- Candidates pursuing a bachelor’s degree in Electrical Engineering or Electrical Engineering Technology are welcome to apply; relevant coursework or project experience is a plus.
- Curiosity about integrated circuits, semiconductor design, or analog and mixed-signal electronics.
- An interest in learning how circuit layouts are planned, built, and verified.
- A thoughtful, problem-solving approach and willingness to ask questions.
- Clear communication and an interest in collaborating with a team.
- Care and attention to detail when working through technical problems.