In this position you will own the verification strategy, testbench development, and sign-off readiness for assigned IPs, subsystems, or distributed systems. You will work closely with Digital Design Engineers and System Architects to identify design defects, close coverage gaps, and drive the adoption of best practices, automation, and scalable verification methodologies across projects. If you enjoy the full lifecycle of digital verification this role is for you.
What you will do
- Own the verification planning process for assigned IPs and subsystems, including definition of verification scope, strategy, coverage goals, and resource requirements
- Develop and maintain reusable verification environments, testbenches, verification components, and infrastructure using industry-standard methodologies and languages
- Ensure complete verification of functional requirements through directed, constrained-random, assertion-based, and coverage-driven verification
- Execute verification closure activities by tracking functional, code, assertion, and other relevant coverage metrics against defined project targets
- Identify, analyze, and drive resolution of design defects through systematic debug and root-cause analysis in collaboration with design engineering teams
- Develop and integrate assertions, checkers, scoreboards, and protocol monitors to improve verification effectiveness and defect detection
- Own regression management, including automation, execution monitoring, failure analysis, and reporting of verification status
- Collaborate with system architects and design engineers to review specifications and ensure verifiable and testable design requirements
- Support verification sign-off reviews by providing objective evidence of verification completeness, risk assessment, and residual defect analysis
- Drive continuous improvement of verification productivity through automation, scripting, tool optimization, and reusable verification assets
- Contribute to the evaluation, qualification, and deployment of new verification methodologies, tools, and technologies
- Ensure verification deliverables meet project milestones while proactively identifying schedule, quality, and technical risks
- Mentor junior verification engineers and provide technical guidance on verification planning, execution, debugging, and best practices
- Bachelor's or Master's degree in Electrical Engineering, Electronics Engineering, Computer Engineering, or a related technical discipline
- 5+ years of experience in digital IC verification within the semiconductor industry
- Strong expertise in SystemVerilog and UVM-based verification methodologies
- Proven experience developing constrained-random, assertion-based (SVA), and coverage-driven verification environments
- Strong understanding of digital design fundamentals, RTL development concepts, and semiconductor development processes
- Hands-on experience with industry-standard simulators, debuggers, and waveform analysis tools
- Demonstrated expertise in functional and code coverage analysis and sign-off methodologies
- Experience debugging complex digital designs and collaborating with cross-functional engineering teams
- Proficiency in scripting languages such as Python or Tcl, with familiarity in version control systems and regression management
- Experience with SoC-level verification and complex subsystem integration projects
- Strong analytical and problem-solving skills with a systematic, detail-oriented approach
- Excellent communication and collaboration skills with the ability to work effectively in global, cross-functional environments
- Self-reliant work style with the ability to take ownership of complex verification tasks end-to-end and proactively identify risks
What you can look forward to:
- Career & Development: Exciting opportunities to grow professionally and personally - in an international environment
- Team Culture: Dynamic, collegial and open to new ideas - together we are writing the future
- Flexibility: Flexible working hours, the option to work occasionally from home
- Mobility: Very good public transport connections and discounted parking with direct access from the office to the garage
- Health & well-being: Company doctor and psychologist - support for your health
- Bonus program: All employees benefit from our success - together we achieve more
- Job bike: Environmentally friendly commuting and staying fit - with us you can lease your bike at a reasonable price
- Events & team building: Summer party, cool team events - we celebrate our successes together
- Employee discounts: From car washes to wellness days - benefit from many discounts
With us you will receive an attractive annual gross salary from 70.000 € (plus bonus, KV Metallgewerbe). Depending on your experience, this can also be higher.
No matter where you are from, how you live, what you believe in - we look forward to receiving your application! What counts for us is the person, not the label. That's why we welcome your unique perspective.
We are committed to equal opportunities and want all applications to be assessed with an open mind. You are welcome to remove your personal information such as age, origin etc. from your CV. We don't need a photo either. This way we can concentrate on the essentials: your qualifications and experience!