About Marvell Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities. At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. Your Team, Your Impact The Central Engineering ASIC Design Services Team within Marvell provides chip solutions for next generation 5G carriers, cloud data centers, enterprise, and automotive applications. As a manager within the ASIC team, you will have the opportunity to lead an experienced team and growing team of physical design, static timing analysis (STA). You will also have the opportunity to interact with customers and the worldwide team to develop solutions to meet our customer’s needs. What You Can Expect As a key member of central physical design team, you will provide backend design service for multiple Marvell SOC design groups, from floor planning, power grid design, place and route, clock tree synthesis, timing closure, power/signal integrity signoff to physical verification (DRC/LVS/Antenna). You will have the opportunity to work on many varieties of challenging designs, i.e. low power and high speed SOCs. You will work closely with frontend and integration team to ensure successful tapeouts. Your responsibility may include participating in cutting-edge physical design methodology and flow development. What We're Looking For BS/MS in EE/CS with 6+ years of hands-on experience in CAD back-end physical design and verification. Familiar with hierarchical physical design strategies, methodologies and deep sub-micron technology issues like N7N5. Familiar with ASIC design flow, Verilog HDL, synthesis and timing closure. Proven track records of handling chip level P&R independently and taping out complex SOC chips under tight schedule pressure. Must be programming-minded, solid coding experience in Makefile/Tcl/Perl. Detail oriented, self-motivated team worker, good verbal and written communication skills. Must be a power user of Cadence suite (Genus, Innovus), Synopsys suite (IC Compiler, fusion compiler). Solid knowledge on static timing analysis (Tempus, or PrimeTime), EM/IR-Drop/crosstalk analysis (Voltus, PTSI, Apache, AstroRail, PrimeRail), extraction (QRC, StarRC), formal or physical verification (LEC, Formality, Calibre) a plus. Good communication skills and self-discipline contributing in a team environment This role is eligible to participate in Marvell's bonus and equity plans, including a new hire equity grant and annual equity refreshers, ensuring you are rewarded for your contributions and remain invested in the company's long-term success. Additional Compensation and Benefit Elements Competitive salary, plus 13th-month salary and performance-based bonus RSUs (Restricted Stock Units) for new joiners and on-going annually Premium health & accident insurance for you and your family (spouse and children) Annual medical check-up at a designated hospital arranged by Marvell Generous paid leave policies: 15 annual leave days, 3 Recharge periods per year (company-wide off-work from Friday to Monday), 5 paid sick leave days, 3 days of volunteer time-off and 11 public holidays Exciting Employee Events: Participate in fun activities throughout the year such as team birthdays, sports tournaments, company trips, mid-autumn, appreciation week, charity, health seminars, year-end party, and more. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status. Interview Integrity To support fair and authentic hiring practices, candidates are not permitted to use AI tools (such as transcription apps, real-time answer generators like ChatGPT or Copilot, or automated note-taking bots) during interviews. These tools must not be used to record, assist with, or enhance responses in any way. Our interviews are designed to evaluate your individual experience, thought process, and communication skills in real time. Use of AI tools without prior instruction from the interviewer will result in disqualification from the hiring process. This position may require access to technology and/or software subject to U.S. export control laws and regulations, including the Export Administration Regulations (EAR). As such, applicants must be eligible to access export-controlled information as defined under applicable law. Marvell may be required to obtain export licensing approval from the U.S. Department of Commerce and/or the U.S. Department of State. Except for U.S. citizens, lawful permanent residents, or protected individuals as defined by 8 U.S.C. 1324b(a)(3), all applicants may be subject to an export license review process prior to employment. #LI-UN1 Join our talent community to hear about company news, job openings and events. Join our Talent Community! Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, automotive, and carrier architectures, our innovative technology is enabling new possibilities. At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. Recruitment fraud is a well-known way that third parties try to get personal information or to steal money from you. Please review Marvell’s guidance here to learn more on how you can protect yourself.

Sr. Staff Engineer, Physical Design.

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