Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.
Role Overview
Astera Labs is establishing a strategic R&D center in Israel to drive the development of complex semiconductor chips that solve the critical 'data bottlenecks' enabling the future of AI at scale. As we expand our presence in Israel, we're seeking a visionary Principal DFT Engineer to help build our local engineering powerhouse from the ground up. This is a unique opportunity to take on meaningful product ownership in a new site, ensuring the reliability and testability of chips that power the world's largest AI clusters.
Key Responsibilities
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Define and own DFT architecture for complex SoCs, including Scan, MBIST, LBIST, JTAG/iJTAG, and ATPG strategies
- Lead DFT planning, specification, and quality tracking across the project lifecycle
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Provide technical leadership and drive DFT sign-off readiness to ensure successful tapeout
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Lead DFT implementation, integration, and verification at block, full-chip and chiplet levels
- Own end-to-end DFT activities from specification through silicon bring-up and production support
- Ensure high test coverage, robust pattern generation, and alignment with manufacturing requirements
- Develop and drive scalable DFT methodologies, flows, and automation frameworks
- Collaborate closely with RTL, Physical Design, STA, and Test Engineering teams to ensure design-for-test readiness
- Optimize DFT integration across front-end and backend flows to improve quality, PPA, and turnaround time
Basic Qualifications
- Bachelor’s degree in Electrical Engineering or related technical field (Master’s preferred)
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12+ years of experience in DFT design, implementation, and verification for complex ASIC/SoC designs
- Proven experience in leading DFT activities across full chip development cycles
- Deep expertise in DFT techniques including Scan, MBIST, LBIST, JTAG/iJTAG, and ATPG
- Strong understanding of DFT and Physical Design flows, including timing implications and integration challenges
- Experience with industry-standard DFT tools (Siemens Tessent, Synopsys TestMAX or equivalent)
- Solid experience with DFT verification methodologies and coverage analysis
- Strong scripting skills (Tcl, Python, or Perl) for automation and flow development
Preferred Qualifications
- Experience with advanced process nodes (7nm and below)
- Background in high-speed connectivity designs (PCIe, Ethernet, CXL, or similar)
- Experience with hierarchical DFT methodologies and large multi-die or chiplet-based systems
- Knowledge of silicon bring-up, production test flows, and yield optimization
- Familiarity with STA, low-power design, and CDC as it relates to DFT integration
- Strong leadership and communication skills, with ability to influence cross-functional teams globally
We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.