What We're Researching
We're running a paid study on modern hardware description workflows and RTL implementation. Our goal is to understand how engineers approach automated evaluation and design verification in complex systems. This research feeds directly into improving tooling and methodologies for hardware development.
How It Works
You will participate in a remote interview to walk us through your typical hardware design process. We will ask you to review specific RTL implementation scenarios and discuss your approach to automated evaluation. You will share your screen to demonstrate how you handle hardware description workflows in practice. The session concludes with a discussion on the challenges you face with current verification tools.
Who This Is For
We are looking for experienced hardware engineers who specialize in RTL design and implementation. We welcome ASIC designers, FPGA engineers, hardware verification specialists, and system-on-chip (SoC) architects. You should have hands-on experience with hardware description languages and automated evaluation frameworks.
What You'll Do
Walk us through your approach to RTL implementation and hardware description
Review and react to specific automated evaluation scenarios
Describe a recent time you tackled a complex hardware verification challenge
Provide feedback on current workflows and tooling gaps
Who Should Apply
Professional experience in hardware engineering or RTL design
Hands-on background with hardware description languages (Verilog, VHDL, or SystemVerilog)
Familiarity with automated evaluation and verification workflows
Comfortable discussing technical design choices in a remote interview
Compensation
$147 per hour
Ready to participate?
About Terac
Terac is building the world's largest pool of vetted human experts for AI. Researchers, AI labs, and product teams use Terac to recruit, screen, and pay study participants across industries, languages, and skill sets.
Learn more at terac.com or on YouTube at @jointerac.