We are seeking a seasoned Backend Design Expert specializing in Static Timing Analysis (STA) and Logic Synthesis. You will own the RTL-to-Gate conversion, constraint development, and final timing closure, ensuring our chips deliver maximum performance at the lowest possible power and area.
Key Responsibilities
- Physical-Aware Synthesis and PPA optimization: Own and execute hierarchical synthesis flows to translate SystemVerilog RTL into optimized gate-level netlists. Execute physical-aware and floorplan-driven synthesis flows to minimize post-layout congestion and achieve PPA targets, identify bottlenecks and drive optimizations (e.g., critical path restructuring, datapath optimization). Conduct flat and hierarchical synthesis, ensuring seamless interface timing budgets. Manage formal verification (LEC) to ensure logical equivalence between RTL and netlist. UPF management for multiply power domains.
- Timing Closure & STA: Perform block-level and full-chip STA across multi-mode and multi-corner (MMMC) scenarios using industry-standard tools. Collaborate with PNR team, understand the clock tree and provide timely feedback to optimize the clock tree and achieve best QOR and perform STA signoff checks to closure.
- Constraint Development: Architect, validate, and manage files, addressing both functional and DFT modes. Develop and manage comprehensive block-level and top-level constraints (SDC / UPF).
- Low-Power Implementation: Implement and verify UPF-based (Unified Power Format) low-power architectures and multi-voltage domains
- Programming/Scripting: Strong scripting skills in Tcl, Python, or Perl to automate flows and improve design methodologies
- Experience of about 8-15 years in synthesis and STA closure.
- Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field.
- Ability to understand design specifications, can contribute to design planning, partitioning, and setup a feasible seed for convergence PD cycle.
- Extensive experience in STA closure on complex design with ability to understand the clocks structure from both functional and DFT side and provide solutions to complete design closure.
- Worked on synthesis of high frequency designs and come up PPA solutions to meet the targets.
- Good understanding of EDA tools such as Fusion Compiler, Innovus, Primetime, Tempus, VCLP, LEC.
- Strong understanding of static timing analysis, power analysis, and signal integrity analysis.
- Excellent problem-solving skills and attention to detail.
- Excellent scripting skills and development of utilities to reduce overall TAT.
- Ability to work effectively in a team environment and communicate clearly with cross-functional teams.
- Experience in mentoring and coaching junior engineers is a plus.
Renesas is an embedded semiconductor solution provider driven by its Purpose, To Make Our Lives Easier. With a global team of over 21,000 engineers and problem solvers in more than 30 countries, we offer the opportunity to work on world‑leading technology for Automotive, Industrial, Infrastructure, and IoT, shaping a safer, healthier, greener, and smarter future.
At Renesas, TAGIE is our culture, grounded in being Transparent, Agile, Global, Innovative, and Entrepreneurial. It shapes how we work, grow and deliver on our purpose together. This collaborative spirit and mindset drive our semiconductor technology to transform industries and impact millions of lives.
We believe in rewarding our employees with a competitive benefits package alongside their salary. More information will be provided during the hiring process.
Are you ready to join our team and shape the future with us?
Renesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. For more information, please read our Diversity & Inclusion Statement.