About Marvell Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities. At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. Your Team, Your Impact As a Principal Engineer-DFT with Marvell, you’ll be a member of the Connectivity business group. Connectivity solutions from Marvell help customers address the growing demands of AI, cloud computing, edge computing, 5G networks, and next-generation data centers. Engineers within the Connectivity Business Unit work on cutting-edge silicon design, firmware, software, system validation, and platform development, collaborating across global teams to deliver products that connect billions of devices and accelerate digital transformation. Joining the Connectivity Business Unit offers the opportunity to work on complex technical challenges, influence next-generation connectivity technologies, and contribute to products deployed at global scale. What You Can Expect Define and drive DFT architecture and implementation strategies for complex SoC/ASIC designs. Develop and implement scan, compression, MBIST, and other DFT features to achieve test coverage and manufacturing quality goals. Execute and support scan insertion, DFT verification, and ATPG flows. Collaborate closely with RTL, verification, physical design, timing, and product engineering teams throughout the design lifecycle. Create and maintain DFT-related timing constraints and signoff requirements. Perform DFT timing analysis and debug timing-related issues. Drive DFT methodology improvements and contribute to flow automation. Provide technical leadership and mentorship to junior engineers. What We're Looking For We are seeking a highly motivated and experienced Principal Engineer – Design for Test (DFT) to lead DFT architecture, implementation, and signoff activities for complex SoC and ASIC designs. The ideal candidate will have deep expertise in DFT methodologies, scan insertion, ATPG, timing constraints, and test architecture development, with a proven track record of delivering high-quality silicon products. Required Qualifications Bachelor's or Master's degree in Electronics Engineering, Electrical Engineering, Computer Engineering, or a related field. 14+ years of experience in Design for Test (DFT) for ASIC/SoC development. Strong expertise in DFT methodologies, including scan architecture, scan compression, ATPG, Memory BIST, Boundary Scan and testability concepts. Hands-on experience with Siemens EDA Tessent tools. Strong experience with synthesis and scan insertion tools. Solid understanding and hands on experience of Static Timing Analysis (STA) and timing closure concepts. Experience creating and managing SDC (Synopsys Design Constraints) files for DFT implementation and timing signoff. Strong debugging, problem-solving, and analytical skills. Excellent communication and collaboration skills. This role is eligible to participate in Marvell's bonus and equity plans, including a new hire equity grant and annual equity refreshers, ensuring you are rewarded for your contributions and remain invested in the company's long-term success. Additional Compensation and Benefit Elements With competitive compensation and great benefits, you will enjoy our workstyle within an environment of shared collaboration, transparency, and inclusivity. We’re dedicated to giving our people the tools and resources they need to succeed in doing work that matters, and to grow and develop with us. For additional information on what it’s like to work at Marvell, visit our Careers page. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status. Interview Integrity To support fair and authentic hiring practices, candidates are not permitted to use AI tools (such as transcription apps, real-time answer generators like ChatGPT or Copilot, or automated note-taking bots) during interviews. These tools must not be used to record, assist with, or enhance responses in any way. Our interviews are designed to evaluate your individual experience, thought process, and communication skills in real time. Use of AI tools without prior instruction from the interviewer will result in disqualification from the hiring process. This position may require access to technology and/or software subject to U.S. export control laws and regulations, including the Export Administration Regulations (EAR). As such, applicants must be eligible to access export-controlled information as defined under applicable law. Marvell may be required to obtain export licensing approval from the U.S. Department of Commerce and/or the U.S. Department of State. Except for U.S. citizens, lawful permanent residents, or protected individuals as defined by 8 U.S.C. 1324b(a)(3), all applicants may be subject to an export license review process prior to employment. #LI-RV1 Join our talent community to hear about company news, job openings and events. Join our Talent Community! Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, automotive, and carrier architectures, our innovative technology is enabling new possibilities. At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. Recruitment fraud is a well-known way that third parties try to get personal information or to steal money from you. Please review Marvell’s guidance here to learn more on how you can protect yourself.

more at Marvell.

26 Oct, 2026

Marvell

Principal Hardware Engineer

Staff level
Engineering

US-CA - Santa Clara, United States of America

Salary not listed

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