About Marvell Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities. At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. Your Team, Your Impact You will be part of Marvell's Central CAD and Design Services (CCDS) organization — the engine that powers every business unit at Marvell. Our team develops and maintains world-class design flows and infrastructure that enable Marvell's semiconductor products across Data Center, Networking, Automotive, and Storage markets. About PSI CAD team: CCDS CAD PSI team is responsible for driving Power Signal Integrity signoff methodology across Marvell's worldwide business units. The team develops and maintains PSI flows within M1DP, supports design teams through tapeout, and collaborates with EDA vendors to continuously improve tool capabilities and methodology. The team operates with a "One Marvell" mindset What You Can Expect Work on block-level and full-chip static IR/EM analysis flow and methodology Work on dynamic IR analysis methodology (vectorless and vector-based using VCD/FSDB) at block and full-chip levels, with and without package models Involved and tuning flows for Out-of-Context (OOC) and In-Context block-level IR analysis Work on Left Shifted IR Analysis like Early Rail Analysis (ERA) to detect power grid weaknesses at floorplan stage Interface with EDA vendors to evaluate new tool features, report bugs, and drive tool improvements. Develop automation scripts (Tcl, Python) to streamline IR/EM flow execution, debug, and reporting. Support tapeout activities by ensuring IR/EM signoff closure across blocks and full-chip designs. Contribute to knowledge sharing, documentation, and training of IR?EM CAD flows across global teams. What We're Looking For B.E./B.Tech or M.E./M.Tech in Electrical Engineering, Electronics Engineering, Computer Science, or a related field. 5+ years of hands-on experience with Cadence Voltus for IR drop and EM analysis in production ASIC/SoC flows Proven track record of running block-level and full-chip PSI signoff on advanced technology nodes (7nm, 5nm, or 3nm) Solid understanding of static/dynamic power and IR Analysis flow & Methodology (including hierarchical) Good understanding of DC & AC-EM analysis and its impact Understanding of package aware IR simulation and chip power model generation flows Understanding of thermal flows is a plus Understanding of multi-die IR/EM analysis is a plus This role is eligible to participate in Marvell's bonus and equity plans, including a new hire equity grant and annual equity refreshers, ensuring you are rewarded for your contributions and remain invested in the company's long-term success. Additional Compensation and Benefit Elements With competitive compensation and great benefits, you will enjoy our workstyle within an environment of shared collaboration, transparency, and inclusivity. We’re dedicated to giving our people the tools and resources they need to succeed in doing work that matters, and to grow and develop with us. For additional information on what it’s like to work at Marvell, visit our Careers page. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status. Interview Integrity To support fair and authentic hiring practices, candidates are not permitted to use AI tools (such as transcription apps, real-time answer generators like ChatGPT or Copilot, or automated note-taking bots) during interviews. These tools must not be used to record, assist with, or enhance responses in any way. Our interviews are designed to evaluate your individual experience, thought process, and communication skills in real time. Use of AI tools without prior instruction from the interviewer will result in disqualification from the hiring process. This position may require access to technology and/or software subject to U.S. export control laws and regulations, including the Export Administration Regulations (EAR). As such, applicants must be eligible to access export-controlled information as defined under applicable law. Marvell may be required to obtain export licensing approval from the U.S. Department of Commerce and/or the U.S. Department of State. Except for U.S. citizens, lawful permanent residents, or protected individuals as defined by 8 U.S.C. 1324b(a)(3), all applicants may be subject to an export license review process prior to employment. #LI-CP1 Join our talent community to hear about company news, job openings and events. Join our Talent Community! Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, automotive, and carrier architectures, our innovative technology is enabling new possibilities. At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. Recruitment fraud is a well-known way that third parties try to get personal information or to steal money from you. Please review Marvell’s guidance here to learn more on how you can protect yourself.

more at Marvell.

26 Oct, 2026

Marvell

Principal Hardware Engineer

Staff level
Engineering

US-CA - Santa Clara, United States of America

Salary not listed

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