Job Description
· Work with semiconductor project teams on chip developments, supporting RTL-to-Gates implementation, static verification, and signoff activities.
· Help project teams adopt and use the production flow through setup, pipe-cleaning, execution, debugging, and basic readiness checks.
· Run project designs, review results, and help resolve issues affecting timing, power, area, runtime, and flow stability.
· Work with design engineers and experienced EDA colleagues to investigate issues involving tools, scripts, constraints, and reports.
· Use project feedback to improve flow automation, reporting, usability, and quality of results.
· Develop and maintain flow infrastructure using industry-standard EDA tools, primarily Synopsys.
· Support migration to the next-generation implementation platform through script porting, validation, testing, and user onboarding.
· Collaborate with project and EDA teams across Europe, India, the US, and Vietnam to share practical experience and consistent working methods.
· Follow good software engineering practices, including version control, modular design, testing, and documentation.
• Bachelor’s or Master’s degree in Electrical/Electronic Engineering, Computer Engineering, Computer Science, or a related technical discipline
• 4+ years of relevant experience in digital implementation, EDA/CAD engineering, or implementation flow development
Technical Experience:
• Practical experience with some aspects of RTL-to-Gates implementation or signoff, such as:
o Synthesis or physically aware implementation
o Static timing analysis and timing closure
o Power or QoR analysis
o Lint, CDC, RDC, or related static checks
• Experience with Synopsys tools is helpful; experience with equivalent industry tools is also welcome
• Scripting or automation experience using Tcl, Python, Perl, or shell scripting
• Familiarity with running and debugging EDA flows in Linux or Unix environments
Useful Additional Experience:
· Experience in one or more of the following areas would be useful:
§ SDC development or timing constraint debugging
§ Clock definitions and clocking strategies
· Awareness of low-power design concepts, including:
o UPF / CPF concepts
o Impact of power intent on implementation and signoff flows
· Exposure to hierarchical or large-scale SoC implementation
· Experience reviewing QoR trade-offs, such as:
o Timing versus area versus power
o Trade-offs across implementation stages and runtime
General Skills:
• Good problem-solving skills and an interest in understanding chip implementation and flow issues
• Comfortable working with project teams in a global, multi-site engineering environment
• Clear written and verbal communication, with a willingness to support and learn from others
• A practical, positive approach and willingness to take ownership of assigned issues
• Interest in learning new tools, technologies, and implementation methodologies
Renesas is an embedded semiconductor solution provider driven by its Purpose, To Make Our Lives Easier. With a global team of over 21,000 engineers and problem solvers in more than 30 countries, we offer the opportunity to work on world‑leading technology for Automotive, Industrial, Infrastructure, and IoT, shaping a safer, healthier, greener, and smarter future.
At Renesas, TAGIE is our culture, grounded in being Transparent, Agile, Global, Innovative, and Entrepreneurial. It shapes how we work, grow and deliver on our purpose together. This collaborative spirit and mindset drive our semiconductor technology to transform industries and impact millions of lives.
We believe in rewarding our employees with a competitive benefits package alongside their salary. More information will be provided during the hiring process.
Are you ready to join our team and shape the future with us?
Renesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. For more information, please read our Diversity & Inclusion Statement.