Energy efficiency remains one of the foremost challenges in modern computing, spanning from edge IoT devices to high-performance data centers. Conventional CMOS-based architectures are approaching fundamental physical limits, while the "memory wall" — data transfers between processor and memory accounting for 70 to 90% of total system energy — continues to worsen with the ever-growing demands of data-intensive workloads such as deep neural networks and signal processing pipelines.
In-Memory Computing (IMC) has emerged as a disruptive paradigm to overcome these bottlenecks by embedding arithmetic operations directly within memory arrays, drastically reducing data movement. In this landscape, ferroelectric field-effect transistors (FeFETs) stand out as particularly compelling devices: fully compatible with standard CMOS fabrication processes, non-volatile, reconfigurable, and capable of storing intermediate polarization states — a property that naturally enables ternary logic within a single device.
The Post-Doctoral position will cover at least one of the following tasks:
Design Standard Cell Technology Library based on FeFET devices developed at INL in order to be used with synthesis flow.
Design and optimize ternary arithmetic units (multiply-accumulate units, adders, comparators) based on the FeFET ternary gate library developed within the project, targeting area, power, and timing closure under realistic process constraints.
Develop and refine system-level models of FeFET-based ternary IMC units, abstracting circuit-level characterization results into architecture simulators, enabling design space exploration across the full heterogeneous system.
Investigate hardware/software co-design strategies for mapping real-world applications — particularly convolutional neural networks (CNNs) and signal processing kernels — onto the ternary IMC fabric, exploiting approximate computing techniques to trade precision for energy efficiency.
Assess and benchmark the energy, performance, and accuracy trade-offs of ternary IMC against binary CMOS and binary NVM-based IMC reference implementations, using both synthetic benchmarks and real application workloads.
Contribute to the definition of a design methodology for ternary ferroelectric circuits, including EDA tool flows, cell library characterization guidelines, and design rules, with the aim of enabling broader community adoption.
Required Candidate Profile
The ideal candidate holds a PhD in microelectronics, computer architecture, or a closely related field, and demonstrates at least one of the following hard skills:
Circuit and architecture design: Strong expertise in digital circuit design flows and computer architecture, with hands-on experience using industrial EDA tools (Cadence Virtuoso/Spectre, Synopsys). Experience with standard-cell library characterization is a plus.
Emerging memory technologies: Solid knowledge of non-volatile memory devices, preferably including ferroelectric materials (FeFET, FeCap) or resistive memories (RRAM, PCM). Familiarity with compact modeling is an asset.
System-level design and simulation: Experience with architecture-level simulation frameworks and hardware/software co-design methodologies. Knowledge of RISC-V ecosystems is a plus.
Application domains: Familiarity with deep neural network inference workloads and/or digital signal processing pipelines, particularly in the context of approximate or energy-constrained computing.
Programming: Proficiency in HDL (Verilog, VHDL, Verilog-A) and scripting languages (Python, Shell) for design automation and simulation.
Soft skills: Scientific leadership, ability to coordinate with PhD students and international partners, strong publication record consistent with career stage, and excellent written and oral communication in English.
Language: Fluent scientific English is mandatory. French is not required but is welcome.