Expert/Senior Logic Design Engineer.

Our client is an innovative technology company developing advanced control and measurement systems for quantum computing. Its hardware and software platforms enable precise, real-time control of complex quantum systems, supporting the evolution of quantum computing from individual qubits to large-scale architectures.

We are looking for an experienced Eхpert/Senior Logic Design Engineer to contribute to the development of next-generation FPGA and ASIC-based control platforms.

In this role, you will design and optimize high-performance digital logic with stringent latency and timing requirements. You will work closely with system architects, verification engineers, software developers, and hardware specialists in an international engineering environment.

Responsibilities

· Design and implement complex, configurable, low-latency RTL modules using SystemVerilog.

· Develop digital logic for high-performance FPGA and ASIC applications, including signal processing, waveform generation, and real-time control.

· Participate in the complete RTL development lifecycle, from architecture and microarchitecture definition to implementation and verification.

· Optimize RTL designs for timing, latency, resource utilization, and power efficiency.

· Perform logic synthesis, timing analysis, and optimization to meet design constraints.

· Collaborate with verification engineers to ensure functional correctness and comprehensive test coverage.

· Analyze system-level and software requirements and implement appropriate hardware-software interfaces.

· Integrate proprietary digital IP into complex FPGA/ASIC architectures.

· Participate in design reviews, debugging, and continuous improvement of engineering processes.

Requirements

· Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related technical discipline, or equivalent practical experience.

· 4+ years of professional experience in FPGA or ASIC digital logic design.

· Strong practical experience in RTL development using SystemVerilog (mandatory).

· Solid understanding of digital logic design, computer architecture, and RTL microarchitecture.

· Experience with logic synthesis, static timing analysis (STA), and timing optimization.

· Practical experience with FPGA or ASIC design and implementation workflows.

· Understanding of clock-domain crossing (CDC), synchronous digital design, and hardware interfaces.

· Experience with simulation-based RTL verification and debugging.

· Strong analytical, problem-solving, and communication skills.

· English proficiency sufficient for effective collaboration within an international engineering team.

Nice to Have

· Experience with AMD/Xilinx FPGA platforms, particularly AMD Versal.

· Experience with AMD Vivado and related FPGA implementation tools.

· Familiarity with Synopsys VCS, Siemens Questa, or equivalent simulation tools.

· Experience with digital signal processing (DSP), waveform generation, or high-speed data acquisition.

· Experience developing deterministic, ultra-low-latency digital systems.

· Familiarity with AXI, PCIe, DDR, or other high-performance hardware interfaces.

· Experience with ASIC-oriented RTL development and reusable digital IP.

· Knowledge of Python, Tcl, or other languages used for development automation.

· Experience with hardware-software co-design and embedded systems.

· Experience in quantum computing, telecommunications, measurement equipment, or other performance-critical digital systems.