About Taara Connect:
Born at X, Google's Moonshot Factory, Taara is on a mission to connect billions of people lacking abundant and affordable internet today by pioneering the way we use light to deliver faster, cheaper, more reliable connectivity. Lead the charge in bringing our groundbreaking wireless optical communication and photonics chip technologies to the world. Drive our growth story as we scale innovative solutions across the world. Join us to light the way for bridging the digital divide and illuminating the future.
Role Overview:
We are seeking a highly-motivated individual that enjoys working in a small dynamic team environment with a passion for solving challenging problems that can lead to high-impact advances in technology. As an FPGA Design Engineer, you will be responsible for the full lifecycle of FPGA designs – design, simulation, implementation, testing, and verification – for digital logic for high-data-rate communications systems and precision line-of-sight tracking systems.
About the Role:
Collaborate across teams to jointly develop high-speed digital signal processing and control system algorithms supporting wireless optical communications applications.
Implement custom RTL modules that enable high data rate communications, as well as timing-sensitive feedback-based precision line-of-sight tracking systems.
Develop test benches for RTL modules, perform simulation, and verify design requirements are met.
Integrate third party IP cores into an FPGA system, create custom RTL wrappers for third party cores, and interface with IP vendors.
Participate in board bring-up activities, system level integration tasks, troubleshooting, and field testing.
Stay current with the latest FPGA technologies, tools, and best practices.
Contribute ideas and participate in improving our design process, infrastructure, and products.
What you should have:
Bachelor of Science in Computer Engineering or similar discipline.
3+ years in FPGA/ Digital Logic Design role, with experience in implementing and testing custom RTL using System Verilog or Verilog.
Experience with FPGA design flow including simulation, synthesis, and static timing analysis.
Experience with FPGA high speed interfaces.
Hands on experience with lab equipment including oscilloscopes and hardware debugging.
Excellent problem-solving and analytical skills.
Strong communication and teamwork skills.
It would be great if you also had these:
MS (or higher) in Computer Engineering, or a related field.
Experience with AMD UltraScale/UltraScale+ FPGAs/SoCs, or equivalent.
Experience coding in embedded C/C++ (or similar) and common scripting languages (e.g. Python, tcl).
Experience implementing RTL blocks for high-speed communications, image processing, and real-time tracking systems.
Experience with Simulink or High Level Synthesis.
The US base salary range for this full-time position is $160,000-$210,000 + bonus + equity + benefits. Our salary ranges are determined by role, level, and location. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific salary range for your location during the hiring process.