Log inSign up free
  • Home
  • Profile
  • Jobs
    • Applications
    • Career
    • Resume
    • Cover letters
  • Content
    • Posts
    • Media
  • Messages
  • Analytics
    • Overview
    • Pages
  • Portfolio
  • More tools
    • Hiring
  • Settings
All jobs
CCCelero Communications logo

Celero Communications

Irvine

Principal DFT Engineer.

STAFF LEVELENGINEERING$200K–240K/YR

Celero Communications is seeking a talented DFT Engineer to join our silicon engineering organization. This individual will partner with design, verification, physical design, product, and manufacturing teams to implement robust Design-for-Test methodologies that enable high quality, high volume production of complex ASIC and SoC products.

What You Will Do

  • Develop and implement DFT architecture for ASIC and SoC designs.
  • Perform scan insertion, scan chain planning, and scan compression implementation.
  • Generate and validate ATPG patterns and analyze fault coverage results.
  • Implement and verify MBIST, and other on-chip test features.
  • Collaborate with RTL, verification, and physical design teams to ensure successful DFT integration.
  • Support JTAG and boundary-scan implementation and debug.
  • Drive DFT signoff activities and manufacturing test readiness.
  • Participate in silicon bring-up, failure analysis, and yield improvement efforts.

What You Will Bring

  • Bachelor’s degree in Electrical Engineering, Computer Engineering, or related field.
  • 8+ years of ASIC/SoC DFT experience.
  • Strong understanding of scan, ATPG, fault models, and test coverage methodologies.
  • Experience with Synopsys TestMAX/TetraMAX, DFT Compiler, Siemens Tessent, Cadence Modus, or equivalent tools.
  • Knowledge of Verilog/SystemVerilog and digital design fundamentals.
  • Experience in Linux and scripting using Python, Tcl, Perl, or Shell.
  • Results-driven engineer with strong debugging abilities.
  • Comfortable working in fast-paced cross-functional environments.
  • Passion for delivering high-quality silicon products.

Preferred Qualifications

  • Experience with advanced-node semiconductor technologies.
  • Hands-on experience with MBIST, compression architectures, and JTAG.
  • Knowledge of timing closure, physical design impacts, and low-power design techniques.
  • Experience supporting silicon validation and manufacturing production ramps.
  • Strong communication and cross-functional collaboration skills.

    Annual Base Salary Range for US: $200,000 - $240,000 (The final offer will be determined based on job-related skills, experience, qualifications, and location.)
Pay
$200k–240k/yr
Where
Irvine · California · United States
Work
Not stated
Type
Not stated
Posted
16 Sep, 2026
Apply on the original postingSign in to apply

Unverified board

more at Celero Communications.

31 Jul, 2026

Celero Communications

Sr. Principal Application Engineer

CCCelero Communications logo
  • Staff level
  • Engineering

$175k–225k/yr

Irvine +2

Details
21 Oct, 2026

Celero Communications

Senior ASIC Design Engineer - DSP/Analog/SerDes

CCCelero Communications logo
  • Senior level
  • Engineering

$150k–250k/yr

Irvine, CA

Details
21 Oct, 2026

Celero Communications

Senior ASIC Design Engineer - DSP/Analog/SerDes

CCCelero Communications logo
  • Senior level
  • Engineering

$150k–250k/yr

San Jose, CA

Details

similar roles.

16 Aug, 2026

Digital Zone

Staff Software Engineer

DZDigital Zone logo
  • Full time
  • Staff level
  • Remote
  • Engineering

United Arab Emirates

Remote

Details
18 Aug, 2026

Digital Zone

Senior Software Engineer - Backend

DZDigital Zone logo
  • Full time
  • Senior level
  • Remote
  • Engineering

United Arab Emirates

Remote

Details
17 Mar, 2025

DAYBREAKER

Event Producer & Community Architect - SAN DIEGO

DADAYBREAKER logo
  • Part time
  • Senior level
  • Remote
  • Engineering

San Diego +2

Remote

Details
27 Jul, 2026

Dalia Consulting

Senior Mechanical Engineer

DCDalia Consulting logo
  • Full time
  • Senior level
  • Engineering

San Francisco +2

Full time

Details
28 Sep, 2026

The Focusrite Group

Support Engineer (Audio Technology) - Linea Research

TFThe Focusrite Group logo
  • Full time
  • Engineering

Letchworth Garden City +2

Full time

Details
28 Sep, 2026

The Focusrite Group

Software Developer Placement - Linea Research

TFThe Focusrite Group logo
  • Full time
  • Engineering

Letchworth Garden City +2

Full time

Details