R&D Engineer.

Responsible for

1. Validate and sanity check existing FPGA protoyping design on hardware.
2. Migrate and optimize existing FPGA prototyping designs to all Synopsys hardware platforms.
3. Create and edit user documents
4. Work in the lab to conduct hardware experiment including maintaining setups and equipment

Responsible for establishing personal timetables according to task assignment and supporting the related assigned project goals of other engineers.

 
Responsible for

1. Validate and sanity check existing FPGA protoyping design on hardware.
2. Migrate and optimize existing FPGA prototyping designs to all Synopsys hardware platforms.
3. Create and edit user documents
4. Work in the lab to conduct hardware experiment including maintaining setups and equipment

Responsible for establishing personal timetables according to task assignment and supporting the related assigned project goals of other engineers.