We’re seeking an experienced engineer to lead bump interconnect development for advanced semiconductor devices (2.5D/3D/chiplet/fan-out).
This role spans ubump and C4 bump metallurgy, RDL design and
plating, chip-side and interposer capture pad design rules, OSAT engagement, reliability,
failure analysis, and cross-functional support through package and system productization.
Core Responsibilities
- Own end-to-end bump interconnect development for both ubump (micro-bump) and C4
processes, including bump formation, and reflow for use with mass reflow, TCB, and LAB chip
attach for high-performance semiconductor packages.
- Define and own bump metallurgy stacks for ubump (e.g., Cu pillar/SnAg) and C4 (e.g., SAC alloys)
interconnects, including UBM selection and pad finish specifications for both chip-side and
interposer capture pads.
- Develop and own design rules for bump interconnects including pitch, bump diameter, standoff
height, keep-outs, and land pad geometry for both the chip side and interposer or substrate
capture pads.
- Lead RDL (redistribution layer) process development including electroplating of Cu RDL traces,
via fills, and pad finishes; define RDL design rules for line/space, via diameter, and layer stack-up
to meet electrical and reliability requirements.
- Collaborate with OSATs and bumping foundries to qualify ubump and C4 bumping processes,
drive design rule alignment, and manage process transfers into production.
- Evaluate and mitigate bump interconnect assembly risks including non-wet opens, voiding, head-
in-pillow, intermetallic growth, and joint fatigue failures across both ubump and C4 interconnect types.
- Perform root cause analysis of assembly and reliability failures using cross-sectioning, SEM,
CSAM, and other failure analysis techniques.
- Support reliability qualification including thermal cycling, drop, mechanical shock, and power cycling.
- Work cross-functionally with design, reliability, thermal, and manufacturing teams to ensure
robust package performance from concept through high-volume production.
Required Technical Skills
- Strong experience in bump interconnect processes including ubump (Cu pillar, micro-bump) and
C4 bumping for semiconductor devices.
- Deep understanding of bumping metallurgy including UBM stacks, solder alloy systems (SnAg),
intermetallic compound (IMC) formation and growth kinetics, and their impact on joint reliability.
- Experience with RDL plating processes including Cu electroplating, photoresist patterning, seed
layer deposition, and associated design rules for line/space, via geometry, and pad stack.
- Understanding of thermo-mechanical behavior in bump interconnect assemblies including CTE
mismatch, warpage, solder joint fatigue, and IMC-driven reliability risks for both ubump and C4
configurations.
- Hands-on experience with failure analysis and reliability testing (cross-sections, SEM, CSAM,
thermal cycling).
- Ability to work with OSATs and suppliers to develop and transfer assembly processes into
production.
- Strong problem-solving skills with ability to debug yield and reliability issues in manufacturing
environments.
Preferred / Differentiating Skills
- Experience with III-V packaging, photonics packaging, and precision chip attach.
- Experience with advanced packaging technologies including 2.5D interposers, 3D stacking,
chiplets, and CoWoS-like architectures.
- Familiarity with fine-pitch micro-bump and hybrid bonding approaches.
- Experience integrating high-power or high-TDP devices with tight warpage and thermal
constraints.
- Exposure to thermo-mechanical modeling or collaboration with simulation teams for warpage
and reliability prediction.
- Understanding of system-level interactions (warpage, second-level interconnect reliability).
- Deep expertise in bump metallurgy fundamentals including UBM stack design (Ti/Cu, etc.), solder
alloy selection, wetting behavior, and the influence of plating chemistry and process conditions
on bump morphology and composition.
- Fundamental knowledge of intermetallic compound (IMC) formation, growth kinetics, and phase
behavior in Cu/Sn, Ni/Sn, and Au/Sn systems; understanding of how IMC thickness, morphology,
and composition affect joint strength, electromigration resistance, and long-term reliability.
Education & Experience:
Industry experience in semiconductor packaging with strong emphasis on bump interconnect
processes, RDL development, and productization.