3D Stacked DRAM Design Engineer.

Job Title: 3D Stacked DRAM Design Engineer
Office Location: San Jose, CA
Job Type: Full-Time
Work Model: Onsite 

Job Summary:

To strengthen leadership in the DRAM-on-Logic era through optimized DRAM die design, we are seeking talent capable of driving the co-design of 3D-stacked DRAM logic dies in close collaboration with U.S.-based customers. This strategic hiring initiative aims to enhance our global competitiveness by fostering deep engagement with key American clients, ensuring that our die design solutions are precisely aligned with their evolving technical requirements and market demands.

Responsibilities:

• Strengthen leadership in the DRAM-on-Logic era through optimized DRAM Die design and technical innovation.
• Co-design 3D-stacked DRAM Logic Dies and next-generation DRAM-on-Logic solutions with U.S.-based customers.
• Design circuits for 3D-stacked DRAM that meet internal and external specifications, including DRAM DFT implementation.
• Review specifications and define the architecture for 3D-stacked DRAM products.
• Improve design quality and yield throughout the 3D-stacked DRAM development phase.
• Enhance performance and ensure stable operation to meet strict customer requirements during product development.
• Establish close technical engagement with key U.S.-based customers to address immediate 3D-stacked DRAM challenges.
• Drive market competitiveness and service differentiation through sustained customer collaboration and technical leadership.

Qualifications:   

• Bachelor’s degree or higher in Electrical Engineering or a related discipline with 4+ years of relevant experience.
• Development of DRAM and design DRAM circuit based on custom design methodology (using virtuoso [or similar tools], spice simulator).
• Experience reviewing DRAM specifications and architecture.
• Circuit design experience to meet internal and external requirements for DRAM products.
• Experience evaluating compliance with DRAM specifications through design analysis at the wafer levels test / package levels test / system level test.
• Experience in full custom + digital Co-design and PDN analysis.
• Experience in full custom-based logic foundry design.
• Expert in Python, and circuit simulators (HSPICE, PrimeSim, Spectre, etc.).
• Excellent verbal and written communication in English; ability to present technical concepts to cross functional teams and senior management.

Benefits:       

• Top Tier health insurance at no employee cost
• Paid day offs: Paid Time Off, Company Holidays, Parental Leave, Happy Fridays
• 401k Matching
• Flexible Spending Account (FSA) for Health Care & Dependent Care
• Educational reimbursement up to $10,000 per year
• Donation Matching and volunteering opportunities
• Corporate discount programs
• Free Breakfast/Lunch/Dinner provided to employees