๐ง๐ต๐ถ๐ ๐ฟ๐ผ๐น๐ฒ ๐ถ๐ ๐ณ๐ผ๐ฟ ๐ผ๐ป๐ฒ ๐ผ๐ณ ๐๐ต๐ฒ ๐ช๐ฒ๐ฒ๐ธ๐ฑ๐ฎ๐'๐ ๐ฐ๐น๐ถ๐ฒ๐ป๐๐
๐ฆ๐ฎ๐น๐ฎ๐ฟ๐ ๐ฟ๐ฎ๐ป๐ด๐ฒ: ๐ฅ๐ ๐ด๐ฌ๐ฌ๐ฌ๐ฌ๐ฌ - ๐ฅ๐ ๐ญ๐ฎ๐ฌ๐ฌ๐ฌ๐ฌ๐ฌ (๐ถ๐ฒ ๐๐ก๐ฅ ๐ด-๐ญ๐ฎ ๐๐ฃ๐)
Experience: 1+ yrs
Location: Hyderabad
We are looking for a detail-oriented and technically skilledย Data Verification Engineerย with hands-on knowledge ofย Verilog and Gate-Level Simulation (GLS)ย to support digital design verification and validation activities. The ideal candidate will have a strong foundation in digital logic, RTL design concepts, simulation methodologies, and hardware verification workflows.
This role is suited for an engineer who is passionate about semiconductor design, functional correctness, and identifying potential issues before hardware implementation. You will work with design and verification teams to validate digital circuits, analyse simulation results, investigate mismatches, and ensure design reliability throughout the development lifecycle.
Requirements
Key Responsibilities
- Develop, execute, and maintain verification test scenarios for digital hardware designs using Verilog-based environments.
- Supportย Gate-Level Simulation (GLS)ย activities using synthesised netlists and appropriate simulation models.
- Analyse RTL and gate-level simulation results to verify design functionality and identify discrepancies.
- Review design specifications and translate functional requirements into verification scenarios.
- Debug simulation failures by analysing waveforms, signal transitions, timing behaviour, and log files.
- Investigate mismatches between RTL and gate-level simulation results and coordinate with design teams to identify root causes.
- Support simulations with timing annotation, including Standard Delay Format (SDF), where applicable.
- Identify potential timing-related issues, including setup and hold violations, glitches, and unknown signal values.
- Work with verification engineers to improve test coverage, testbench quality, and simulation reliability.
- Execute regression tests and maintain accurate records of test results, failures, and verification status.
- Assist in debugging issues related to reset sequences, clock behaviour, signal connectivity, and logic functionality.
- Collaborate with RTL Design, Physical Design, and Verification teams to resolve design and simulation issues.
- Maintain technical documentation, verification reports, and debugging notes.
- Follow established verification methodologies, coding standards, and project quality processes.
What Makes You a Great Fit
- 1+ year of experienceย in digital design verification, semiconductor engineering, or a related hardware design role.
- Strong foundational knowledge ofย Verilog HDLย and digital logic design.
- Familiarity withย Gate-Level Simulation (GLS)ย and the simulation of synthesised netlists.
- Understanding of RTL design, combinational and sequential logic, clocks, resets, and timing concepts.
- Familiarity with simulation tools such asย Cadence Xcelium, Synopsys VCS, or Siemens Questaย is an advantage.
- Basic understanding of SDF annotation, timing checks, and simulation mismatches.
- Ability to analyse simulation logs and waveforms using waveform viewers and debugging tools.
- Familiarity with Linux environments, command-line tools, and basic scripting is beneficial.
- Strong analytical, debugging, and problem-solving skills with attention to detail.
- Good communication skills and the ability to collaborate effectively with cross-functional engineering teams.
- A bachelor's or master's degree in Electronics Engineering, Electrical Engineering, VLSI, Computer Engineering, or a related discipline is preferred.