Our Physical Design group operates in a dynamic, startup-like environment that values deep technical expertise and high-level execution. Each engineer holds end-to-end responsibility - from initial definition and constraints development to execution and full signoff. You will work closely with Design and Architecture teams on RTL modifications and design reviews to ensure seamless convergence.
We’re looking for a Physical Design Engineer to join our growing team, and take a key role in developing our next-generation SoC from definition to Tape-Out.
What will your job look like:
- Hands-on physical design block owner, leading the process from RTL to GDS.
- Lead floorplan exploration in collaboration with Front-End and Architecture teams.
- STA: Partner with FE and floor planners to manage block and top-level constraints and perform 1st-level timing analysis.
- Synthesis: Conduct synthesis exploration and deliver final netlists, including scan insertion, UPF, and clean Lint/Spyglass checks.
- Place & Route: Drive the flow from synthesis netlist to final layout and signoff verification, with a focus on optimizing PPA (Power, Performance, and Area).
- Signoff: on all physical design domains- STA, IR/EM, Physical Verification, Logic Equivalent Checking, Low Power Verification.
All you need is:
- BSc or MSc in Computer Engineering or Electrical Engineering.
- 0-2 years of experience in the industry.
- Proficiency in scripting languages (Tcl, Python, Perl, or tcsh).
- A team player with excellent communication skills and a “can-do” attitude.
Nice to have:
- Experience in developing or maintaining implementation tools and design flows.
- Experience with high-speed interfaces (DDR/PCIE).
- Experience with advanced nodes (5nm and below).
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