About Etched
Etched is building hardware for frontier intelligence. We co-design chips, racks, software, and manufacturing to deliver best-in-class throughput and latency across both prefill and decode workloads. Our first products are heavily focused on inference. Backed by hundreds of millions from top-tier investors and staffed by leading engineers, Etched is redefining the infrastructure layer for the fastest growing industry in history.
What you'll do
Own HAPS bring-up. Take RTL from the design teams and get it running on the prototype — partitioning, multi-FPGA timing closure, clocking, memory mapping, and full-chip assembly.
Expand platform coverage. Stand up new subsystem configurations so more of the chip is available to software earlier. Each new partition you enable unblocks a team.
Support your users. Firmware, driver, and software engineers are your customers. You'll help them get running, triage their failures, and figure out whether the bug is theirs, the RTL's, or the platform's.
Debug hard problems. Trace issues across FPGA boundaries with waveform capture, protocol analyzers, and whatever tooling you have to build yourself.
Bring up interfaces. PCIe, Ethernet, HBM and memory models, JTAG, I2C, UART, QSPI — both the models and the physical bridges.
Build the flows. Automate builds, regressions, and image delivery so the platform scales past the number of people who understand it.
Work across the org. Design, DV, Silicon Validation, Performance, Firmware, and Software — plus direct partnership with Synopsys on tool issues and platform capability.
Representative projects
Bring up a new subsystem partition on HAPS and get firmware booting on it end to end.
Build a self-service flow that lets software users load and run their own images without prototyping support in the loop.
Instrument deep trace capture across partition boundaries and build the tooling that surfaces it usefully.
Create configurable chip-to-chip and off-chip interface models using prototyping-efficient primitives.
Close timing on a partition that doesn't want to close, and document how you did it so the next person doesn't have to rediscover it.
You may be a good fit if you have
Hands-on FPGA prototyping experience — HAPS, Protium, proFPGA, S2C, or similar — covering partitioning, synthesis, timing closure, bring-up, and debug.
Strong SystemVerilog and Verilog, with a working understanding of what synthesizes well for FPGA and what doesn't.
Solid C/C++ and Linux system development.
Scripting fluency for automation — Python, TCL, shell.
Comfort debugging failures you didn't cause, in code you didn't write, for users who need an answer today.
Strong candidates may also have
Experience with ProtoCompiler, Vivado, or Synopsys prototyping flows.
Firmware, driver, or bootloader bring-up experience on pre-silicon platforms.
Experience with emulation platforms (ZeBu, Palladium, Veloce) alongside prototyping — we run both, and the collateral is shared.
UVM verification environments, DFT, and testbench modeling.
Waveform debug tooling: Verdi, SimVision.
Cluster and job scheduling experience (SLURM), CI systems.
Benefits
Medical, dental, and vision packages with generous premium coverage
$500 per month credit for waiving medical benefits
Housing subsidy of $2,500 per month for those living within walking distance of the office
Relocation support for those moving to San Jose (Santana Row)
Various wellness benefits covering fitness, mental health, and more
Daily lunch and dinner in our office
Unlimited compute budget subject to ROI justification
Compensation Range
$150,000 - $275,000
How we’re different
Etched believes in the Bitter Lesson. We are the first inference-focused frontier AI system. Our addressable market is the entirety of inference, unlike many of our competitors.
We are a fully in-person team in San Jose (Santana Row), and greatly value engineering skills. We do not have boundaries between engineering and research, and we expect all of our technical staff to contribute to both and work across disciplines as needed.