Log inSign up free
  • Home
  • Profile
  • Jobs
    • Applications
    • Career
    • Resume
    • Cover letters
  • Content
    • Posts
    • Media
  • Messages
  • Analytics
    • Overview
    • Pages
    • Events
  • Portfolio
  • More tools
    • Hiring
  • Settings
All jobs
ALAstera Labs logo

Astera Labs

Taipei, Taiwan

Lead HVM Product Engineer.

LEADENGINEERING

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.

 

Job Description:

As an Astera Labs HVM Product and Test Engineering, you will support existing products already in HVM (high volume manufacturing) at our Asia OSAT partners. Maintaining smooth manufacturing to ensure on-time customer shipments is one key objective. In this role, you will complement the New Product Introduction Product Engineers as products are released into production and own the engineering manufacturing during mass production. The ideal candidate possesses breadth of industry experience in high-speed product development in the field of product and/or test engineering, can apply fundamentals in circuit, ATE, and test program to aid problem solving, and is a self-driven, result focused go-getter in the pursuit of goals and objectives.

Basic qualifications:

· Minimum of 5 years of experience in the field of post silicon product development dealing with high-speed XCVR (product, test or validation)

· Experience in product and package qualification

· Have gone through at least one cycle of full product development life cycle

· Strong academic/technical background in electrical or computer engineering; Bachelor’s is required; MS preferred

· Strong problem-solving skills that involve system level analysis with test hardware, test program and DUT.

· Digital and analog circuit level understanding for DUT.

· Excellent team player with great communication skills

· Professional attitude with the ability to prioritize a dynamic list of multiple tasks

Required experience:

· Proven track record continuing seamless production of semiconductor products partnering with OSATs supporting high volume manufacturing through the complete product lifecycle

· Hands on experience with using the Advantest 93k ATE platform with specific skills updating ATE test programs for wafer sort and final test solutions

· Familiarity with JEDEC standard and hands on experience in product and package qualification, failure disposition, FIT rate calculation

· Detailed mindset monitoring device ATE test yields, ATE test time, device quality and rolling out new ATE test programs using consistent BKMs

· Strong data analysis skills using tools such as JMP or Spotfire calculating limits and drawing conclusions

· Energetic work mindset meeting the demands of shipping quality parts to Astera Labs’ customers through the manufacturing stage of development

Preferred experience:

· Working with silicon validation teams to ensure device performance meets production requirements.

· Firmware development in C/C++, scripting in Python, or other equivalent programming experience.

· Hands-on knowledge of NRZ/PAM4 SerDes protocols like PCIe (Gen3 and above), Ethernet (25G and above), etc. and/or memory interfaces such as (LP)DDR5/4.

 

We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

Pay
Not stated
Where
Taipei, Taiwan
Work
Not stated
Type
Not stated
Posted
29 Aug, 2025
Apply on the original postingSign in to prepare an application

Verified board

more at Astera Labs.

13 Oct, 2026

Astera Labs

Tech Lead Analog Mixed-Signal IC Layout Engineer

ALAstera Labs logo
  • Lead
  • Engineering

Singapore, Singapore

Salary not listed

Details
13 Oct, 2026

Astera Labs

Teach Lead Physical Design Engineer

ALAstera Labs logo
  • Lead
  • Engineering

Singapore, Singapore

Salary not listed

Details
13 Oct, 2026

Astera Labs

Senior Manager, Global Safety & Security

ALAstera Labs logo
  • Lead
  • Security

$180k–230k/yr

San Jose +2

Details

similar roles.

13 Oct, 2026

Core One

Field Engineer - Junior

COCore One logo
  • Junior level
  • Engineering

$70k–95k/yr

Sterling, VA

Details
13 Oct, 2026

The National Football League

Seasonal Associate Producer

TNThe National Football League logo
  • Temporary
  • Junior level
  • Engineering

Mount Laurel +2

Temporary

Details
13 Oct, 2026

Immersive

Senior Solutions Architect - UAE

IMImmersive logo
  • Full time
  • Senior level
  • Remote
  • Engineering

UAE

Remote

Details
13 Oct, 2026

Illumio

Sr. Escalation Engineer

ILIllumio logo
  • Full time
  • Senior level
  • Remote
  • Engineering

$160k–192k/yr

South Carolina - Remote +2

Details
13 Oct, 2026

Illumio

Sr. Sales Engineer

ILIllumio logo
  • Full time
  • Senior level
  • Remote
  • Engineering

JPY 12.4M–15.5M/yr

Tokyo, Japan

Details
13 Oct, 2026

Gen Digital

Junior Engineer - Working Student Thesis

GDGen Digital logo
  • Full time
  • Junior level
  • Engineering

CZE - Brno

Full time

Details