At Kandou, we are redefining the economics of AI infrastructure. Our mission is to democratise AI by significantly reducing the Total Cost of Ownership (TCO) of hardware systems — a critical barrier to scalable adoption.
Our proprietary MIMO-over-copper technology powers a high-performance, chiplet-based AI memory fabric that is both scalable and energy-efficient. Unlike traditional interconnects, our solution reduces power consumption significantly while preserving high bandwidth and ultra-low latency — unlocking unprecedented efficiency for AI training and inference at scale.
Kandou’s architecture is not just an incremental improvement — it’s a foundational shift in how AI hardware is built for the future.
Job Title: Director of Silicon Characterization
Location: Saint-Sulpice, Switzerland
Responsibility
Own the silicon characterization strategy and execution for multiple product programs, from first silicon through validation closure and release readiness.
Lead development of comprehensive validation plans, schedules, resource allocation, and execution tracking across projects and locations.
Oversee development of scripts, automation frameworks, and program infrastructure for IC validation, characterization, and ATE interfacing.
Ensure rigorous and timely execution of silicon bring-up, debug, validation, and characterization for SerDes-based and other high-speed products central to Kandou AI’s portfolio.
Drive the definition, specification, and review of evaluation boards and reference hardware required for lab validation and customer enablement.
Support customer demos, technical evaluations, and issue resolution involving silicon, EVMs, and validation data.
Co-own silicon validation, characterization, and test reporting, ensuring clear communication of status, risks, correlation, and readiness.
Partner closely with design, product engineering, quality, applications, and operations teams to accelerate debug cycles and improve silicon learning.
Required Skills
Strong understanding of validation and characterization requirements for high volume semiconductor products and IP.
Ability to define validation coverage from product specifications and translate it into structured test plans, milestones, and resource plans.
Effective collaboration with analog, digital, DfT, product, and applications teams to review and finalize validation strategy.
Ability to lead teams and coordinate execution across multiple sites and external partners.
Sound judgment in selecting methods, tools, and trade-offs for technical problem solving.
Experience evaluating lab and test equipment, managing vendors, and supporting procurement decisions.
Good understanding of budgeting, lab investment planning, productivity, and cost management.
Flexible, pragmatic, and execution-oriented when addressing unexpected silicon or lab issues.
Required Experience
10+ years of experience in the semiconductor industry, with deep expertise in IC bring-up, validation, characterization, and ATE interface development.
Strong hands-on experience in high-speed or high-frequency signal measurement, lab automation, and validation environments.
Proven expertise with instruments and methods used for electrical and compliance testing, including BERTs, oscilloscopes, and signal analyzers.
Experience with SerDes-based products is strongly preferred and especially relevant for Kandou AI’s technology roadmap.
Good understanding of high-speed multilayer reference PCB or evaluation board design for products with demanding signal integrity requirements.
Experience supporting customers through evaluation, debug, demonstrations, or product adoption activities.
Education
Bachelor´s or Master’s degree in Electronic Engineering or relevant field.
www.kandou.ai