EnCharge AI is a leader in advanced AI hardware and software systems for edge-to-cloud computing. EnCharge’s robust and scalable next-generation in-memory computing technology provides orders-of-magnitude higher compute efficiency and density compared to today’s best-in-class solutions. The high-performance architecture is coupled with seamless software integration and will enable the immense potential of AI to be accessible in power, energy, and space constrained applications. EnCharge AI launched in 2022 and is led by veteran technologists with backgrounds in semiconductor design and AI systems.
Staff Engineer: STA Methodology & Sign-off Lead
We are seeking a high-caliber Staff or Senior Staff Engineer to architect and lead our SOC Static Timing Analysis (STA) Methodology along with execution responsibilities to eliminate the bottle-necks in STA and build bridges.
This is a critical role for a forward-thinking engineer who excels at defining the frameworks and flows required to navigate the complexities of modern, large-scale SOC designs. Engineer will have scope to bridge Architecture, CAD, RTL, and Physical Design to establish a predictable, high-performance, and scalable path to tape-out.
The Role As the lead for STA Methodology, you will own the sign-off architecture and the timing convergence strategy. Rather than just executing runs, you will build the "engine" that enables execution—defining flows, qualifying tools, establishing margin strategies (AOCV/LVF/POCV), and driving cross-functional alignment to meet aggressive Power, Performance, and Area (PPA) targets.
Key Responsibilities
- Sign-off Methodology & Architecture: Define and own full-chip SOC timing sign-off criteria, including Multi-Mode Multi-Corner (MMMC) definitions, derate strategies, and operating condition mapping for functional, shift, and capture modes.
- Flow Development & Left-Shift Automation: Architect, deploy, and maintain advanced STA and ECO flows. Develop methodologies to proactively identify structural timing issues and predict physical design bottlenecks early in the RTL/Synthesis phases.
- Tool Benchmarking & Deployment: Evaluate, qualify, and deploy new EDA tool features and capabilities (with a strong emphasis on Cadence Tempus) to improve Quality of Results (QoR), optimize memory/runtime efficiency, and streamline hierarchical timing models.
- Custom Automation Infrastructure: Architect scalable, robust automation utilities (Tcl, Python, Perl) to standardize constraint (SDC) management, automate cross-domain timing audits, and accelerate the ECO loop across distributed design teams.
- Cross-Functional Enablement: Partner with Physical Design to define optimal clock tree synthesis (CTS) methodologies and floorplanning guidelines. Guide DFT and RTL teams on methodology to resolve structural bottlenecks (e.g., NoC timing, complex CDC paths).
Requirements & Qualifications
- Experience: 8 to 11 years of hands-on experience in VLSI design, with a primary focus on STA Methodology, flow development, and sign-off criteria at advanced process nodes (7nm, 5nm, or below).
- Technical Mastery:
- Deep expertise in building flows around industry-standard sign-off tools, with a strong preference for Cadence Tempus.
- Mastery of Multi-Mode Multi-Corner (MMMC) flow architecture, Hierarchical (ILM/ETM) vs. Flat timing strategies, and constraint (SDC) validation methodologies.
- Strong understanding of advanced node timing phenomena, including waveform propagation, crosstalk, and statistical margining (LVF/POCV).
- Critical Thinking: Proven ability to architect broad flow solutions and debug systemic tool or methodology bottlenecks, rather than just fixing isolated timing violations.
- Soft Skills: Strong leadership presence with the ability to define technical standards, influence cross-functional teams, and drive methodology adoption in a fast-paced, high-growth environment.
- Education: B.Tech/M.Tech in Electrical/Electronics Engineering or a related field.